As called a memory wall problem, a time period required for memory access and electric power consumption act as major factors hindering the performance enhancement of an arithmetic core.
As a remedy for this problem, a countermeasure is taken to, for example, make a capacity of a cache memory with a higher speed than that of a main memory larger. In the past, a static RAM (SRAM) with a higher speed than that of a dynamic random access memory (DRAM) used as the main memory has been often employed as the cache memory. However, it is more difficult to achieve high integration in the SRAM than the case of the DRAM. Moreover, cost of the SRAM is high. Accordingly, making the capacity of the cache memory larger leads to a problem such as an increase in a circuit area and a rise in the cost.
A next generation memory other than the SRAM is also researched as the cache memory. For example, a magnetoresistive RAM (MRAM) with a higher speed than that of the DRAM is also researched as the cache memory. The MRAM is a non-volatile memory where the high integration can be achieved relatively with ease. Additionally, leakage electric power is low in the MRAM and thus electric power saving can be realized. However, the MRAM is considered to be inferior to the SRAM from a viewpoint of access speed because the MRAM has a slower speed than that of the SRAM particularly during writing.